Most low voltage electronic systems have a few different DC supply voltages providing the regulated power to various electronic functional blocks. Switched power supply regulator circuits are commonly employed, because of their high efficiency. One of the most popular types of switched power supply regulator circuit, for example, that converts an input DC voltage into a lower level output voltage for the functional circuitry, is the DC-to-DC synchronous buck converter.
The efficiency of a DC-DC converter is determined by the power dissipated in its power stage, and in its driver and controller circuit. The driver circuit can be implemented separately as a specialized IC, or it can be integrated into one package with the controller circuit. Power MOSFETs switching in a complementary mode are popular devices used as the switches in the DC-DC synchronous buck converter power stage. Such MOSFETs convert the DC input voltage into periodic pulses which, after filtering by a low pass filter, form the DC output voltage at a lower level determined by the duty cycle. An example 10 of such a converter circuit is shown in FIG. 1. Circuit 10 has a power stage 12 with a control MOSFET 13, a synchronous MOSFET 14, a control circuit 15 and a drive circuit 16.
In the converter circuit 10, the input voltage Vin is intermittently applied to an inductor L that provides an energy storage function, under control of control MOSFET 13 that acts as a switch under control of a driver circuit 16. A control circuit 15 provides a pulse input to the driver circuit 16, and the driver circuit 16, in turn, applies two complementary sets of gate drive pulses to the power MOSFETs, control FET 13 and synchronous FET 14, respectively. The synchronous MOSFET 14 closes a circuit loop during the OFF times of control FET 13, thereby allowing inductor L to discharge the energy stored during the ON time of control FET 13. Input capacitor Cin provides a filtering function by bypassing high frequency components, such as spikes, generated as a result of the “chopping” action on the DC input voltage Vin. Output capacitor Cout provides a filtering function to smooth the output voltage Vout, which is provided at a lower level than that of Vin.
The sets of pulses output by driver circuit 16 for the power stage MOSFETs both have amplitude Vdr. The pulses for the control MOSFET 13 have a duty cycle D, while the pulses for the synchronous MOSFET 14 have a duty cycle (I-D), as shown in FIG. 2. The duty cycle D is set by the control circuit 15, to thereby regulate the output voltage Vout at the required level.
In multi-phase configuration, the power stage 12 and driver circuit 16 are multiplied in accordance to the number of phases, while one control circuit distributes phase shifted control pulses to drivers in each phase, thus accomplishing lower spike and ripple current through the input and output filter capacitors Cin and Cout, respectively. A schematic of a multi-phase synchronous buck DC-to-DC converter 30 of this type is shown in FIG. 3. Converter 30 may be built from commercially available ICs. The particular chipset shown in the figure supports up to four DC-to-DC converters, with only two being shown for clarity. Pin designations are conventional, for example PWMn(n=1, 2, 3, 4) referencing the pulse width modulated pulsed outputs of control circuit IC 31, PWM referencing the pulse width modulated pulsed input for driver circuit ICs 32 and 33, UGATE and LGATE referencing the gate drive pulses for the “upper,” i.e., control MOSFET and “lower,” i.e., synchronous MOSFET, respectively, and CS referencing current sense signals, for auxiliary control circuitry (not shown) such as current limit, for example.
The efficiency of a DC-to-DC converter is an important issue that needs to be addressed by the circuit designer. As mentioned above, the efficiency of a DC-to-DC converter is determined by the power dissipated in its power stage, for example stage 12 of converter 10, and in the drive and control circuits, for example units 16 and 15, respectively, of converter 10. As a general matter, the power dissipation, Pcond, of the power stage is influenced by the resistance Rds(on) of the switches, e.g., MOSFETs 13 and 14 of converter 10. Specifically:Pcond=Irms2×Rds(on)  Eq. (1)where Irms is the root mean square current through the switch. The drain to source resistance of MOSFETs in their ON state, Rds(on), is inversely proportional to their drive, i.e. gate-to-source, voltage Vgs. Consequently, a higher drive voltage results in less power being dissipated by the power stage of the converter. Typical curves illustrating how the Rds(on) of power MOSFETs depends on the drive voltage applied between their gate and source are shown in FIG. 4.
Examining this in more detail, the power Pdr dissipated by the drive circuit 16 can be expressed in equation form. The voltage applied to the gate of the MOSFET depends on the charge delivered to the gate. This dependence is shown graphically in FIG. 5. For a given drive (gate to source) voltage Vgs, the power dissipated by the driver circuit is proportional to the drive voltage of the MOSFET, to the gate charge Qgs of the MOSFET and to the switching frequency Fsw:Pdr=Vgs×Qgs×Fsw.  Eq. (2)The gate charge of the MSOFET is given by the following equation:Qgs=Cgs×Vgs,  Eq. (3)where Cgs is the gate to source capacitance of the MOSFET. Thus, the driver losses are proportional to the square of the gate-to-source voltage:Pdr=Cgs×Vgs2×Fsw.  Eq. (4)Comparing Equation (1) for the MOSFET conduction losses, Pcond, with Equation (4) for the driver losses, Pdr, it can be seen that there is an optimal drive voltage that provides the lowest power losses and highest efficiency for the synchronous buck converter in a selected load current range. This is illustrated graphically in FIG. 6 for three different gate-source (drive) voltages, 5V, 7V and 12V, where the graph is a plot of converter efficiency, as a percentage, against load current. The curve where the drive voltage is 7V provides the highest efficiency in a broad current load range, and is shown by a dashed line curve in the graph.
Input supply voltages, readily available in the typical power distribution system, are standardized, and they are not available for the highest efficiency drive voltage. For example, a 5V drive voltage, shown by an alternating long dash, short dash line curve in the graph, results in lower efficiency at the maximum load current. On the other hand, a 12V drive voltage, shown by a solid line curve in the graph, has low efficiency at middle range to light loads. Moreover, at higher drive voltages, such as 12V, the driver IC dissipates an increasing, and significant amount of power as the switching frequency and number of driven MOSFETs increase. This can result in temperature overstresses inside the driver IC. In some applications, the input voltage that is available varies in a wide range, so it cannot be used directly as the supply voltage for the driver circuit because it may exceed the safe operating region of the driver, or degrade the overall efficiency of the converter.
It would therefore be desirable to increase the overall efficiency of DC-DC synchronous buck converters across a wide load current range, to decrease the power dissipated by the driver circuit in such converters, and to increase the reliability of such driver circuits, without sacrificing the efficiency across the wide load current range. It would, of course, also be desirable that any solution meeting these objectives be simple and inexpensive.
Straightforward approaches to meeting these objectives, involving adding an additional power supply to generate the required optimal drive voltage from the available input supply voltage, are possible. If a high-efficiency switching DC-to-DC converter is used to solve the problem, it is expensive. One of the more popular and relatively low cost solutions uses a linear power supply, and is shown in FIG. 7.
The circuit 70 shown in FIG. 7 may be provided in an IC that is external to the driver IC. However, in many cases a more complex, integrated version of a linear regulator is placed inside the driver IC for convenience. However, this solution has several drawbacks. First, it dissipates additional power, approximately 50% of the power that could be saved if the optimal drive voltage were readily available. Second, it requires that the input supply voltage be higher than the optimal drive voltage, which may be an unacceptable limitation. Third, in cases where the linear regulator is integrated into the driver IC, the additional dissipated power limits the switching frequency of the converter and the number of MOSFETs that can be driven. Finally, the integrated version requires a more expensive package for the driver IC because of this increased dissipated power, the higher voltage devices used inside the chip, and the extra pins that need to be added for the input and output of the linear regulator.
An alternative approach is to use a more efficient DC-to-DC converter to generate an optimized drive voltage. Basically, this involves replicating the circuit shown in FIG. 1, but designing it for much lower power than the main DC-to-DC converter. However, such an approach is expensive.